Видео с ютуба Open Instruction-Set Architecture

AIMP 06: Christian Stenzel on the Future of Open AI Hardware

Can Chip Design Really Be Open Source? | SSSC Science Salon #124

RISC-V: The open processor architecture we deserve

Learn to Build ChatGPT AI Agents (Complete Masterclass)

In depth overview of RISC V, an Open Standard Instruction Set Architecture ISA

[LCTES'25] R-Visor: An Extensible Dynamic Binary Instrumentation and Analysis Framework for Open(…)

GROW 2025 - Open EDA Tools and Design Methodologies

GROW 2025 - Software Stack and Runtime Systems + Panel: Open Source and Open Hardware

Is this the End of Graphene OS? | Changes to AOSP and the Impact on Custom ROMs

RISC-V open designs and contributions to hardware security research and development activities

Open Source Chip Design in the European Semiconductor Strategy

Towards Open-Source and Automatic Performance Characterization Hardware

From Open Silicon to Sovereign Supercomputing: EuroHPC’s Vision for RISC-V

Open-Source Xiangshan Nanhu Processor Experience Day

Utilizing RISC-V Trace Standards for Efficient Bugfixing and Profiling